As the operating voltages for CMOS transistor circuits have decreased, variations in the threshold voltages for the transistors have become more significant. Although low operating voltages offer the potential for reduced power consumption, threshold voltage variations due to process and environmental variables often prevent optimum efficiency and performance from being achieved due to increased leakage currents.
Prior Art FIG. 1A shows a conventional CMOS inverter 100. A P-type substrate 105 supports an NFET 110 and a PFET 120. The NFET 110 comprises a gate 112, source 113, and drain 114. The PFET 120 resides in an n-well 115, and comprises a gate 122, drain 123, and a source 124. The substrate 105 and source 113 are coupled by a tie 130 that is connected to ground (GND), while source 124 and N-well 115 are coupled by a tie 135 that is connected to a supply voltage (VDD). The input to the inverter is applied to the gates 112 and 122, with the output taken from the drain contact 125. In this conventional configuration, the transistors are often treated as three terminal devices.
Threshold voltage variations may be compensated for by body-biasing. Body-biasing introduces a reverse bias potential between the bulk and the source of the transistor that allows the threshold voltage of the transistor to be adjusted electrically. The purpose of body-biasing is to compensate for 1) process variations; 2) temperature variations; 3) supply voltage variations; 4) changes in frequency of operation; and 5) changing levels of switching activity.
Prior Art FIG. 1B shows an inverter having connections for body-biasing. Body-bias can provided to the PFET 120 through a direct bias contact 150a, or by a buried n-well 140 using contact 150b. Similarly, body-bias may be provided to the NFET 110 by a surface contact 155a, or by a backside contact 155b. An aperture 145 may be provided in the buried n-well 125 so that the bias potential reaches the NFET 110. In general, a PFET 120 or an NFET 110 may be biased by one of the alternative contacts shown.
Depending upon the environmental and operational conditions, a CMOS circuit may require different levels of bias for the transistors. For example, a microprocessor that is executing a computationally intensive routine for a real-time application will typically be biased for maximum speed, whereas during periods of low activity the bias will be adjusted to minimize leakage current.
For a CMOS integrated circuit, the load presented to a circuit providing a body-bias voltage and the bias circuit itself may vary with the environmental and operational conditions of integrated circuit. Thus, the variations in the required body-bias voltage and the load to which it is applied should be taken into account to achieve optimum performance.